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(R)
CMOS STATIC RAMs 64K (16K x 4-BIT)
Added Chip Select and Output Controls
IDT7198S IDT7198L
Integrated Device Technology, Inc.
FEATURES:
* Fast Output Enable (OE) pin available for added system flexibility * Multiple Chip Selects (CS1, CS2) simplify system design and operation * High speed (equal access and cycle times) -- Military: 20/25/35/45/55/70/85ns (max.) * Low power consumption * Battery back-up operation--2V data retention (L version only) * 24-pin CERDIP, high-density 28-pin leadless chip carrier, and 24-pin CERPACK packaging available * Produced with advanced CMOS technology * Bidirectional data inputs and outputs * Inputs/outputs TTL-compatible * Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7198 is a 65,536 bit high-speed static RAM orga-
nized as 16K x 4. It is fabricated using IDT's high-performance, high-reliability technology--CMOS. This state-of-theart technology, combined with innovative circuit design techniques, provides a cost effective approach for memory intensive applications. Access times as fast as 20ns are available. The IDT7198 offers a reduced power standby mode, ISB1, which is activated when CS1 or CS2 goes HIGH. This capability decreases power, while enhancing system reliability. The low-power version (L) also offers a battery backup data retention capability where the circuit typically consumes only 30W when operating from a 2V battery. All inputs and outputs are TTL-compatible and operate from a single 5V supply. The lDT7198 is packaged in either a 24-pin ceramic DlP, 28-pin leadless chip carrier, and 24-pin CERPACK. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0 VCC GND DECODER 65,536-BIT MEMORY ARRAY
A13 I/O0 I/O1 I/O2 I/O3
COLUMN I/O INPUT DATA CONTROL
CS1 CS2 WE1 OE
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY TEMPERATURE RANGE
(c)1994 Integrated Device Technology, Inc.
MAY 1994
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DSC-1027/4
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IDT7198S/L CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
MEMORY CONTROL
The IDT7198 64K high-speed CMOS static RAM incorporates two additional memory control features (an extra chip select and an output enable pin) which offer additional benefits in many system memory applications. Both chip selects, Chip Select 1 (CS1) and Chip Select 2 (CS2), must be LOW to select the memory. If either chip select is pulled HIGH, the memory will be deselected and remain in the standby mode. This dual chip select feature (CS1, CS2) also brings the convenience of improved system speeds to the large memory designer by reducing the external logic required to perform decoding.
PIN DESCRIPTIONS
Name A0-A13
CS1 CS2 WE OE
Description Address Inputs Chip Select 1 Chip Select 2 Write Enable Output Enable Data I/O Power Ground
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I/O0-I/O3 VCC GND
PIN CONFIGURATIONS
A0 A1 A2 A3 A4 A5 A6 A7 A8
CS 1 OE
TRUTH TABLE(1)
Mode
CS1 CS CS2 WE OE
I/O High-Z High-Z DOUT DIN High-Z
Power Standby Standby Active Active Active
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1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20
D24-1 E24-1
19 18 17 16 15 16 15
VCC A13 A12 A11 A10 A9
CS2
Standby Standby Read Write Read
H X L L L
X H L L L
X X H L H
X X L X H
I/O3 I/O2 I/O1 I/O0
WE
NOTE: 1. H = VIH, L = VIL, X = don't care.
GND
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DIP/SOJ/CERPACK TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TA Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Mil. -0.5 to +7.0 -55 to +125 -65 to +135 -65 to +150 1.0 50 Unit V C C C W mA
INDEX
A0 NC NC VCC NC
TBIAS TSTG
3
2
A1 A2 A3 A4 A5 A6 A7 A8 CS 1
4 5 6 7 8 9 10 11
1
28 27 26 25 24 23
L28-2
22 21 20 19
18 12 13 14 15 16 17
NC A13 A12 A11 A10 A9 I/O3 I/O2 I/O1
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PT IOUT
NOTE: 2985 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OE GND CS 2 WE I/O 0
LCC TOP VIEW
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IDT7198S/L CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0 -- -- Max. Unit 5.5 0 6.0 0.8 V V V V
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Military Ambient Temperature -55C to +125C GND 0V VCC 5V 10%
2985 tbl 06
CAPACITANCE (TA = +25C, f = 1.0MHz, VCC = 0V)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 0V VOUT = 0V Max. 7 7 Unit pF pF
NOTE: 2985 tbl 05 1. VIL (min.) = -3.0V for pulse width less than 20ns, once per cycle.
NOTE: 2985 tbl 04 1. This parameter is determined by device characterization, but is not production tested.
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V 10%, Military Temperature Range Only
IDT7198S Symbol |ILI| |ILO| VOL Parameter Input Leakage Current Output Leakage Current Output Low Voltage Test Condition VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 10mA, VCC = Min. IOL = 8mA, VCC = Min. VOH Output High Voltage IOH = -4mA, VCC = Min. -- 2.4 Min. -- -- Max. 10 10 0.5 0.4 -- IDT7198L Min. -- -- -- -- 2.4 Max. 5 5 0.5 0.4 -- V
2985 tbl 07
Unit A A V
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2
2985 tbl 10
5V 480 DATAOUT 255 30pF*
5V 480 DATAOUT 255 5pF*
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Figure 1. AC Test Load
Figure 2. AC Test Load (for tCLZ1, 2, tOLZ, tCHZ1, 2, tOHZ, tOW and tWHZ) *Includes scope and jig capacitances
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IDT7198S/L CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5V 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7198S20 7198L20 Symbol ICC1 Parameter Operating Power Supply Current, CS1 and CS2 VIL, Outputs Open VCC = Max., f = 0(2) Dynamic Operating Current, CS1 and CS2 VIL, Outputs Open VCC = Max., f = fMAX(2) Standby Power Supply Current (TTL Level), CS1 or CS2 VIH, VCC = Max., Outputs Open, f = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS1 or CS2 VHC, VCC= Max., VIN VHC or VIN VLC, f = 0(2) Power S L S L S L S Military 105 80 160 130 70 50 25 7198S25 7198L25 Military 105 80 155 120 60 40 20 7198S35 7198L35 Military 105 80 140 115 50 35 20 7198S45 7198S55/70 7198S85 7198L45 7198L55/70 7198L85 Military 105 80 140 110 50 35 20 Military 105 80 140 110 50 35 20 Military 105 80 140 105 50 35 20 mA mA mA Unit mA
ICC2
ISB
ISB1
L
1.5
1.5
1.5
1.5
1.5
1.5
2985 tbl 06
NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
DATA RETENTION CHARACTERISTICS OVER MILITARY TEMPERATURE RANGE
(L Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Typ. (1) VCC @ Symbol VDR ICCDR tCDR(3) tR(3) |ILI|
(3)
Max. VCC @ 2.0V -- 600 -- -- 2 3.0V -- 900 -- -- 2 Unit V A ns ns A
2985 tbl 09
Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Input Leakage Current
Test Condition --
CS1
Min. 2.0 -- 0 tRC(2) --
2.0v -- 10 -- -- --
3.0V -- 15 -- -- --
or CS2 VHC VIN VHC or VLC
NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization but is not production tested.
LOW VCC DATA RETENTION WAVEFORM
DATA RETENTION MODE VDR2V VIH VDR VIH
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VCC t CDR CS
4.5V
4.5V tR
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IDT7198S/L CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, Military Temperature Range)
7198S20 7198L20 Symbol Read Cycle tRC tAA tACS1,2 tCLZ1,2 tOE tOLZ
(2) (2) (1) (2)
7198S25 7198L25
7198S35/45 7198L35/45
7198S55 7198L55
7198S70 7198L70
7198S85 7198L85
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle Time Address Access Time Chip Select-1,2 Access Time Chip Select-1,2 to Output in Low-Z Output Enable to Output Valid Output Enable to Output in Low-Z Chip Select 1,2 to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change Chip Select to Power Up Time Chip Deselect to Power Down Time
20 -- -- 5 -- 5 -- -- 5 0 --
-- 19 20 -- 9 -- 8 8 -- -- 20
25 -- -- 5 -- 5 -- -- 5 0 --
-- 25 25 -- 11 -- 10 9 -- -- 25
35/45 -- -- 5 -- 5 -- -- 5 0 --
--
55
-- 55 55 -- 35 -- 20 20 -- -- 55
70 -- -- 5 -- 5 -- -- 5 0 --
-- 70 70 -- 45 -- 25 25 -- -- 70
85 -- -- 5 -- 5 -- -- 5 0 --
-- 85 85 -- 55 -- 30 30 -- -- 85
ns ns ns ns ns ns ns ns ns ns ns
2985 tbl 11
35/45 -- 35/45 -- -- 5
20/25 -- -- 14 15 -- -- 5 -- -- 5 0
tCHZ1,2 tOHZ tOH tPU tPD
(2) (2) (2)
35/45 --
NOTES: 1. Both chip selects must be active low for the device to be selected. 2. This parameter is guaranteed by device characterization but is not production tested.
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC ADDRESS tAA
OE
tOH
tOE tOLZ
CS1,
(5)
tOHZ
(5)
2
tACS1, 2 tCLZ1, 2 DATAOUT
(5)
tCHZ1, 2 DATA VALID
(5)
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NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is LOW. 3. Address valid prior to or coincident with CS1 and or CS2 transition LOW. 4. OE is LOW. 5. Transition is measured 200mV from steady state voltage.
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IDT7198S/L CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATA VALID DATA VALID
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tOH
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
CS1,2
tACS1, 2 tCLZ1, 2 (5) DATAOUT tPU VCC SUPPLY CURRENT ISB ICC DATA VALID
tCHZ1, 2
(5)
tPD
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NOTES: 1. WE is HIGH for Read cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is LOW. 3. Address valid prior to or coincident with CS1 and or CS2 transition LOW. 4. OE is LOW. 5. Transition is measured 200mV from steady state voltage.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, All Temperature Ranges)
7198S20 7198L20 Symbol Write Cycle tWC tAW tAS tWP tWR1,2 tWHZ tDW tDH tOW
(2) (2)
7198S25 7198L25
7198S35/45 7198L35/45
7198S55 7198L55
7198S70 7198L70
7198S85 7198L85
Parameter Write Cycle Time Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Write Enable to Output in High-Z Data Valid to End-of-Write Data Hold Time Output Active from End-of-Write
Min. Max. Min. Max. Min. 17 17 17 0 17 0 -- 10 0 5 -- -- -- -- -- -- 5/6 -- -- -- 20 20 20 0 20 0 -- 13 0 5 -- -- -- -- -- -- 7 -- -- -- 30/40 25/35 25/35 0 25/35 0 -- 15/20 0 5
Max. Min. Max. Min. Max. Min. Max. Unit -- -- -- -- -- -- -- -- -- 50 50 50 0 50 0 25 0 5 -- -- -- -- -- -- 25 -- -- -- 60 60 60 0 60 0 -- 30 0 5 -- -- -- -- -- -- 30 -- -- -- 75 75 75 0 75 0 -- 35 0 5 -- -- -- -- -- -- 40 -- -- -- ns ns ns ns ns ns ns ns ns ns
2985 tbl 12
tCW1,2(1) Chip Select to End-of-Write
10/15 --
NOTES: 1. Both chip selects must be active low for the device to be selected. 2. This parameter is guaranteed by device characterization but is not production tested.
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IDT7198S/L CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 7) WE
tWC ADDRESS
OE
tAW
CS1,
2
tAS
WE
tWP (7)
tWR
tWHZ (6) DATAOUT
(4)
tOW
(6) (4)
tDW DATAIN
tDH
DATA VALID
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TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)(1) CS
tWC ADDRESS tAW
CS1,
2
tAS
WE
tCW
tWR
tDW DATAIN DATA VALID
tDH
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NOTES: 1. WE, CS1 or CS2 must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW WE, a LOW CS1 and a LOW CS2. 3. tWR is measured from the earlier of CS1, CS2 or WE going HIGH to the end of the write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, outputs remain in the high-impedance state. 6. Transition is measured 200mV from steady state. 7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
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IDT7198S/L CMOS STATIC RAM 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
ORDERING INFORMATION
IDT7198 Device Type X Power XX Speed X Package B Process/ Temperature Range B Military (-55C to +125C) Compliant to MIL-STD-883, Class B 300 mil Ceramic DIP (D24-1) Leadless Chip Carrier (L28-2) CERPACK (E24-1)
D L E
20 25 35 45 55 70 85
Military Only Military Only Military Only Military Only Military Only Military Only Military Only
Speed in nanoseconds
S L
Standard Power Low Power
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